The official HWBOT OC Challenge October 2011 thread.

[PizzaMan]

Think stage 2 looks a little buggy, maybe it's just me...

[basco]

i think stage 2 should only be ddr2.

[Luebke]

yeah in the whole competition is ddr2 completely useless becaus of ddr3 is best in all stages except the first one...
next time maybe this way:
stage 1: sdr
stage 2: ddr1
stage 3: ddr2
stage 4: ddr3
stage 5: so-dimm

[Rasparthe]

Nah, should have included CAS 1 and CAS 3 and removed CAS 10.

[I.nfraR.ed]

Guys from HWBOT staff, could you take a look at my score and the comments, please.

Definitely it's not CL4, but it's the same for other boards, we can't tell all of them. You should take a decision about this stage. There might be problems with detection in other stages as well.

[Don_Dan]

I already sent a PM regarding stage 2 to Massman three days ago, but I'll repost it in public.
I had a hard time believing all the CL4 scores that have been posted, so I checked some datasheets from both Elpida and Micron:

Micron D9GTR Datasheet, page 111:
CAS Latency (CL):
The CL is defined by MR0[6:4], as shown in Figure 53 on page 109. CAS latency is the
delay, in clock cycles, between the internal READ command and the availability of the
first bit of output data. The CL can be set to 5, 6, 7, 8, 9, or 10. DDR3 SDRAM do not
support half-clock latencies.

Also, right at the beginning it says:
• CAS (READ) latency (CL): 5, 6, 7, 8, 9, 10, or 11
• POSTED CAS ADDITIVE latency (AL): 0, CL - 1, CL - 2
• CAS (WRITE) latency (CWL): 5, 6, 7, 8, based on tCK

Then I checked Elpida's datasheets, I think the correct MGH-E datasheet is not available, so I had a look at the one for EDJ1108BASE in general. Right at the beginning it says:
• /CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11
• /CAS Write Latency (CWL): 5, 6, 7, 8

Seems like CL4 is not supported by DDR3 at all and the boards are running at some other CAS Latency. I know some guys think those clocks are real, but please show me CL5 at those clocks, it should be easy, right?

I heard some guys are also hoping for CL2 on DDR2, here's an excerpt from a Micron DDR2 datasheet:
CAS Latency (CL):
The CAS latency (CL) is defined by bits M4–M6, as shown in Figure 36 (page 79). CL is
the delay, in clock cycles, between the registration of a READ command and the availability
of the first bit of output data. The CL can be set to 3, 4, 5, 6, or 7 clocks, depending
on the speed grade option being used.
DDR2 SDRAM does not support any half-clock latencies. Reserved states should not be
used as an unknown operation otherwise incompatibility with future versions may result.

[Mr.Scott]

So basically what you're saying is

CAS 2 = DDR
CAS 4 = DDR2
CAS 6,8,10 = DDR3

[Don_Dan]

Yes.

[knopflerbruce]

Sounds reasonable - DDR2 for CL4

[Mr.Scott]

Excellent. I concur.