The Stilt's Book of Bulldozer - Revelations: Episode 2 (SuperPI / x87)
Posted over at XtremeSystems but so incredibly epic that it needs to be as here as well. All credit for the work goes to The Stilt who seems to be able to kick pretty much every R&D team in the industry (including AMD's own). This is the BEST I have seen in overclocking for a LONG-LOOOOONG time and beats 99,99% of the "world record" or live OC competition events achievements as far as I'm concerned. This makes DDR3-4400 look like child's play ... this is what overclocking is all about: .
Exactly two year ago, when I tested a Bulldozer based Zambesi CPU for the first I was shocked.
The early sample units were even hotter and slower than the final silicon revision CPUs, which finally were released four months later.
One of the largest single let-down came from the way back: SuperPI.
SuperPI mainly uses legacy x87 instructions which have been almost completely superceded. SuperPI doesn't show any indication what so ever about SMP performance as it can only utilize a single thread. On top of that it has no real world use or purpose as there are newer programs which can calculate PI almost 100 times faster.
Still, SuperPI can almost be considered as a industry standard.
Nowdays it is generally a VERY poor indicator of real world performance, yet it is so addictive for any old school overclocker. It scales very well along with the CPU/NB/DRAM/IO performance and tweaking it is a big challenge. An overclocker who hasn't ever benched SuperPI simply doesn't exist.
SuperPI has a special place in my heart simply because it was one of the first benchmarks I ever ran... almost 14 years ago...
So, why are all of the 15h (Bulldozer) based CPU/APU/NPUs performing so bad in SuperPI? Some people say it is because 15h family has 50% less FPs per core than the preceeding 10h family.
In 15h family a compute unit (two cores) share a FP when the 10/12h family had a dedicated FP for each of the cores. If this would be the only reason, the issue would be solved when the "slave" core of the CU is disabled, leaving a "private" FP for the "master" (BSC) core. However this is not the case and it even shouldn't be as SuperPI is single threaded, remember?
The caches on 15h family have higher latency than 10h family for example, and SuperPI happens to love large & low latency caches.
15h family was initially designed for high frequencies. Just like the F1 engines, they produce no power at low revs. And unfortunately it currently doesn't seem to be possible to build an engine capable reving high enough. We might discuss more about the caches in "Episode 3"... If possible.
Agner Fog from Copenhagen University College of Engineering has made an excellent document about the instruction latencies of the modern CPUs.
Values for 10h family start from page 26, while 15h family values are located at page 36.
Few days when I was doing some low level testing for other purposes, I found something that didn't make any sense to me.
Now I roughly know what it is and what it does, but still some questions remain: Why does this "feature" exist in the first place and why it is activated on all 15h family parts. I would normally assume it is a workaround for some errata, however no bulletin exists for this one either. Also this feature does not exist in any documentation, or it does but only AMD has access to the required level. I find it hard to believe that it would be a design issue as the affected instructions work fine (but slowly) and it existed since early Zambesi revisions and, currently is still present in Richland and probably beyond (within family 15h)...
I'd say it is either a errata fix or a errata fix gone wrong. If it is a programming mistake which has gone un-noticed during the last two years ... That would make me just sad.
Effect: A massive performance hit in application heavily utilizing x87 instructions.
Negative effects: TBD, none found yet. The performance in non x87 applications remains the same or improves very slightly. No instability, increased power consumption, reduced overclockability or anything else abnormal has been observed. However the final conclusion requires far more extended testing than I am able to do myself.
After the fix has been applied SuperPI shows 18-30% improvement in performance. Bigger the calculation, bigger the improvement. Since this kind of fix is quite unheard of, I knew that I would be crucified if I would make such claims without any providing evidence.
I generally hate to do videos however this time it was mandatory. I apologize the quality, 1080p is available but the quality is quite grainy due poor lightning. It was a cloudy day in Helsinki today.
The video shows few important things:
In the video the fix is called as "The Plow of Bulldozer"
SuperPI 1.5 XS Mod validated by online MD5 checksum
CPU-Z 1.64.3 x32 validated by online MD5 checksum (can be found from Stasio's CPU-Z thread)
The clocks are being shown during the calculation (look for the affinity and CPU-Z core selection)
An external clock reference is provided (to prove there is no tampering with the timers, i.e. "Lab Burst" by MSI)
The air cooled setup is shown and so are the CPU temperatures (HWMonitor)
39 seconds better time with stock CPU clocks (4.1GHz, NB 2500, MEMCLK DDR-2400) than on 5GHz Trinity with 2777MHz NB and DDR-2666 memory clocks.
Since I 'happened' to have some LN2 in my disposal, I decided to do some high clock SuperPI runs on Richland.
AMD 32nm SuperPI 32M record taken easily. Tomorrow when I throw in a Vishera, the reign of 10h should be finally over
All of the runs are either completely or partially on video.
Will upload them once I have time to edit them. I've been filming around 28GB worth of video during the last 48h hours.
Here's his fastest -ever AMD SuperPI 1M
And then the software is almost ready
Originally Posted by The Stilt
There are two kind of news bad and good ones.
Let's get rid of the bad ones first:
Originally I tested this fix on three different CPU/APUs (Richland, Trinity and Vishera).
When I went to verify the effects of the fix on Zambezi the system crashed immediately once the necessary changes were written.
After some research I noticed that these registers do not respond on Zambezi based CPUs.
Upon reading all of them return null values and crash the system unless a special method is used.
At first it appeared that these registers do not exist on Zambezi, however after digging a bit deeper I found indication that the registers are there... But for some reason AMD seem to have protected them with a ESI/EDI password on Zambezi.
They do not require any passwords on any Piledriver based APU/CPU.
So the fix will not be available for Zambezi users.
Sorry for the massive let-down
The the good news:
The software is pretty much finished.
It should be available for download within this week.
After the let-down on Zambezi I felt that something had to be done for Zambezi too.
While it does not result as massive boost as the original fix does it still gives something:
SuperPI 1M: > 1 second improvement
SuperPI 8M: > 10 second improvement
SuperPI 32M: > 35 second improvement
It is called as "Zambezi Stack Special (PD)".
Note: There might also be some performance specialbunnyation in some applications when enabled (Zambezi vs. Vishera effect).
Zambezi is significantly faster than Vishera in SuperPI by default so the difference between a "fixed" Vishera and a tuned Zambezi won't be that massive after the "Zambezi Stack Special" configuration.
Where courage, motivation and ignorance meet, a persistent idiot awakens.